In memory systems including multiple non-volatile memory chips, error detection and correction is a commonly known issue. In particular, emerging non-volatile memory (NVM) devices, known as storage class memories, are intended to replace or complement conventional technologies, i.e. DRAM and variants, in building future memory systems. The typical architecture of contemporary memory systems consists of multiple memory chips which are put together in a memory module (DIMM). Such architectures ensure high capacity, high bandwidth, as well as very high reliability. The latter is achieved because of the very high reliability of individual DRAM chips, and the possibility to spread information across multiple chips, and therefore be able to tolerate random or burst errors with relatively simple error correction codes.
One possible memory system is volatile storage based on DRAM chips, which are extremely reliable devices, guaranteed to provide ultra-low raw bit error rates (BER) by refreshing their contents at short intervals. On the other hand, non-volatile storage based on NVM devices are rather un-reliable because of high raw BER, but they do not require refresh to retain data. The objective in future memory systems is to use NVM to replace or complement DRAM in order to leverage the superior capacity and cost/GB of these NVM technologies. However, the higher raw BER of such NVMs presents a very challenging problem which has to be overcome in order to build highly reliable memory systems.
One solution is to employ very strong error correction codes (ECC) to protect against the increased random and burst errors of NVMs. Error detection and corrections systems are for example disclosed in US 2014/0181618 A1 or U.S. Pat. No. 8,533,558 B2.
In DIMM architectures the user data is spread across a pre-defined number of chips, and an ECC parity is stored in additional chips, which are reserved for that purpose. However, when using stronger ECC, more extra chips can be needed to store the parity. This results in several critical technical issues. In particular, the bus width in today's DIMMs is fixed and can not be easily extended and more signals from more chips require additional buffer ASICs on the DIMM, which can result in signal integrity problems. Also, important business issues can arise since the memory-module industry and system manufacturers are unwilling to adopt non-standard solutions.
Accordingly, the present invention provides a multi-chip device and a method for storing data and improving the bit error rates during the detection and/or decoding of the stored data.